Search This Blog

Loading...

CS2354 Advanced Computer Architecture Anna university Question paper for ME(Master of engineering)

Wednesday, April 6, 2011 ·


M.E/M.Tech DEGREE EXAMINATION, JUNE 2010
First Semester
Computer Science and Engineering
CS9211 – COMPUTER ARCHITECTURE
(Common to M.Tech - Information Technology)
        (Regulation 2009)
Time: Three hours                                                                               Maximum: 100 Marks
                                                     Answer all the questions
                                                    Part A – (10*2=20 Marks)
1.      State the principle of locality and its types.
2.      What are the choices for encoding instruction set.
3.      What is speculation? Give an example.
4.      Mention the effects of imperfect alias analysis.
5.      What is loop unrolling?
6.      Give the uses of sentinel.
7.      Define multiprocessor cache coherence.
8.      What are the approaches used for multithreading?
9.      Which block should be replaced on a cache Miss?
10.  How is cache performance improved?
    Part B – (5*16=80 Marks)
11.  (a)(i)Explain the operations designed for media and signal processing. (10)
    (ii)Explain the ways in which a computer architect can help the compiler writer. (6)
                                                            (Or)
(b)(i)Discuss the addressing modes used for signal processing instructions. (7)
     (ii)Describe the addressing modes and instructions designed for control flow. (9)

12.  (a)Explain the techniques to overcome data hazards with dynamic scheduling. (16)
(Or)
(b)Describe the limitations of Instruction level Parallelism. (16)

13.  (a)(i)Explain the basic VLIW approach used for static multiple issues. (8)
    (ii)Enumerate the crosscutting issues in hardware and s/w speculation mechanisms. (8)
                                                            (Or)
(b)(i)Explain the hardware support for exposing more parallelism at compile time. (8)
    (ii)Describe the basic compiler techniques for exposing ILP. (8)
14.  (a)(i)Describe the design challenges in SMT processors. (8)
    (ii)Discuss the performance of shared memory multiprocessors. (8)
                                                            (Or)
(b)(i)Explain synchronization mechanisms designed for large scale multiprocessors. (9)
    (ii)Discuss the details of memory consistency models. (7)

15.  (a)(i)Explain the concept of miss penalty and out of order execution in processors. (6)
    (ii)Discuss the methods of interface between CPU and memory. (10)
                                                            (Or)
(b)Discuss in detail the different levels of RAID. (16)

1 comments:

Dhilip Prabakaran said...
January 8, 2013 at 7:35 AM  

This is not a BE CSE Question Paper !!! SPAM !!! Delete it Please !!!

Post a Comment